In producing an active matrix liquid crystal display device, after a display panel is assembled such that an active matrix substrate is combined with a counter substrate (CF substrate) and a liquid crystal is injected therebetween, inspecting of faults in produced wiring lines is carried out by an illumination inspection of a display panel before driving circuits of the display panel such as a scanning signal line driving circuit and a signal line driving circuit and a control circuit are mounted.
FIG. 6 illustrates a configuration of a test circuit of a liquid crystal display panel disclosed in Patent Document 1.
The liquid crystal display panel illustrated in FIG. 6 is arranged such that an active matrix substrate 116 is combined with a counter substrate 118, and a liquid crystal is injected therebetween. An effective display region 117 in a region where the active matrix substrate 116 overlaps the counter substrate 118 is usable for providing view images, and light from a backlight (not shown) can pass therethrough. A region except for the effective display region 117 in the region where the active matrix substrate 116 overlaps the counter substrate 118 is light-shielded by the counter substrate 118.
The active matrix substrate 116 includes a blank region that does not overlap the counter substrate 118, around a set of two adjoining edge sides of the liquid crystal display panel. A data signal line driving circuit 120a is mounted in a region of one of the two edge sides of the blank region, and a scanning signal line driving circuit 120b is mounted in a region of the other one of the two edge sides of the blank region.
In the active matrix substrate 116, a test display signal line 121 and test TFTs 126a that are switching elements for data line test are provided opposite to the data signal line driving circuit 120a such that the effective display region 117 is sandwiched therebetween, and a test scanning signal line 122 and test TFTs 126b that are switching elements for scanning line test are provided opposite to the scanning signal line driving circuit 120b such that the effective display region 117 is sandwiched therebetween.
Drains of the test TFTs 126a are respectively connected to data lines 103 and all sources of the test TFTs 126a are connected to the test display signal line 121 in common. Gates of the test TFTs 126a are respectively connected to a red test control signal line 125R, a green test control signal line 125G, and a blue test control signal line 125B, each provided as a control signal line for data line test, such that colors of the data lines 103 connected to the test TFTs 126a respectively correspond to colors of the control signal lines 125R, 125G, and 125B for data line test. Signals are respectively supplied to the control signal lines 125R, 125G, and 125B for data line test from test input terminals (hereinafter referred to as test terminals) 130R, 130G, and 130B while a signal is supplied to the test display signal line 121 from a test terminal 132. The test terminals 130R, 130G, and 130B are provided in the blank region of the active matrix substrate 116.
Further, drains of the test TFTs 126b are respectively connected to scanning lines 102 and all sources of the test TFTs 126b are connected to the test scanning signal line 122 in common. Gates of the test TFTs 126b are connected to a control signal line 124 for scanning line test. A signal is supplied to the control signal line 124 for scanning line test from a test terminal 141, and a signal is supplied to the test scanning signal line 122 from a test terminal 139. Further, storage capacitor lines 104 are provided on the active matrix substrate 116, and a signal is supplied to the storage capacitor lines 104 from a test terminal 143. The test terminals 139, 141, and 143 are provided in the blank region of the active matrix substrate 116.
Moreover, (i) a plurality of terminals p, which are connected to wires to the scanning signal line control circuit 120b or a counter substrate signal input terminal 127 provided in the blank region, and (ii) a plurality of terminals q, which are connected to wires to the data signal line driving circuit 120a, are provided on an edge side of the blank region of the active matrix substrate 116. Furthermore, the test terminal 127 is connected to a common transition section 119.
An illumination inspection of the liquid crystal display panel having the configuration is carried out as follows. Predetermined signals are supplied to the counter substrate signal input terminal 127 and the test terminal 143 so that voltages of a counter electrode and the storage capacitor lines 104 are set. A signal is supplied from the test terminal 141 so as to cause all the test TFTs 126b to be in an ON state, and then a signal is supplied from the test terminal 139 so that all the scanning lines 102 are caused to be in a selection state. Meanwhile, signals are supplied from the test terminals 130R, 130G, and 130B so as to cause the test TFTs 126a, respectively corresponding to colors of the test terminals 130R, 130G, and 130B, to be in an ON state, so that a signal inputted from the test terminal 132 is supplied to the data lines 103 via the test TFTs 126a in the ON state.
As such the illumination inspection is carried out with each of the KGB colors being displayed. This makes it possible to easily carry out a visual detection of not only a bright spot, but also a dark spot that is a leakage defect between a picture element electrode and a data line 103 that should not supply a signal to the picture element electrode (the data line 103 generally supplies a signal to an adjoining picture element), a leakage defect between adjacent picture elements, and a leakage defect between data lines 103 and 103.
Further, Patent Document 2 discloses a configuration in which (i) a test array having TFTs that are connected so as to short-circuit between scanning lines and (ii) a test array having TFTs that are connected so as to short-circuit between signal lines are provided outside a display region, and an inspection is carried out such that all the TFTs of these arrays are caused to be on so that displaying images can be carried out entirely on a panel.
FIG. 7 illustrates a test circuit structurally similar to the aforementioned test circuit.
The test circuit is different from the one of FIG. 6 in that test data signals can be set depending on KGB colors and all switching elements (the after-mentioned test TFTs 201b) that control whether or not the data signals are supplied to data lines are limited such that all the switching elements are caused to be simultaneously ON or OFF.
As illustrated in FIG. 7, in a liquid crystal display panel including the test circuit, a test wiring region 201, an excess region 202, a dummy pixel region 203, and an effective display region 204 are placed in this order in a direction in which data lines extend. The test wiring region 201, the excess region 202, and the dummy pixel region 203 are placed in a frame area (peripheral area) and light-shielded by a counter substrate. The effective display region 204 corresponds to an effective display region 117 in FIG. 6.
The effective display region 204 is arranged such that pixels are placed in regions surrounded by scanning lines Gj (j is an integer) and data lines Si (i is an integer) that are provided perpendicularly to each other. FIG. 8 illustrates an exemplary configuration of the pixels. In FIG. 7, for the sake of convenience in illustration, pixel electrodes of the pixels in the effective display region 204 are represented by P, and pixel electrodes of dummy pixels are represented by DP.
Each pixel includes a TFT (SW) whose gate is connected to a scanning line Gj, and whose source is connected to a data line Si, and a pixel capacitor Cp one of whose electrodes is connected to a drain of the TFT (SW). The other electrode of the pixel capacitor Cp is connected to a common electrode wire that is common to all the pixels. The pixel capacitor Cp is constituted by a liquid crystal capacitor CL and a storage capacitor Cs that is additionally provided as necessary.
In the test wiring region 201, three test data lines (first lines) 201R, 201G, and 201B, each corresponding to R, G, or B color, which are provided in a parallel direction to the scanning lines Gj, a test switch line (a second line) 201a that is provided parallel to the test data lines 201R, 201G, and 201B, and test TFTs (switching elements) 201b are provided. A circuit that is constituted by the test data lines 201R, 201G, and 201B, the test switch line 201a, and the test TFTs 201b is a first circuit. The test switch line 201a is singularly placed nearer to the effective display region 204 than the test data lines 201R, 201G, and 201B, and a common control signal for electrical connection and disconnection is supplied to the test TFTs 201b via the test switch line 201a. The test TFTs 201b are respectively provided for the data lines Si so as to be connected to the test data lines 201R, 201G, and 201B such that the test data lines 201R, 201G, and 2013 respectively correspond to colors of the data lines Si. The test TFTs 201b achieve electrical connection and disconnection between the data lines Si and the test data line 201R, 201G, and 201B. Further, gates of the test TFTs 201b are connected to the test switch line 201a. 
The excess region 202 is a region to which numbering is carried out for forming a pattern 202a so that the pattern 202a indicates where each line per pixel width along the data lines Si is located from an end.
In the dummy pixel region 203, pixels are provided structurally equivalent to the pixels in the effective display region 204. The pixels in the dummy pixel region 203 may be provided in a plurality of rows, and gates of TFTs (SW) of pixels provided nearest to the effective display region 204 are connected to a dummy scanning line DG. The dummy scanning line DG is provided so as to have an effect on pixels in the effective display region 204, which pixels are provided nearest to the frame area, in a similar manner that an adjacent scanning line Gj has a parasitic capacitance effect on other pixels in the effective display region 204. From the same viewpoint, the entire dummy pixels are arranged in a similar manner to the pixels in the effective display region 204 so that all the pixels in the effective display region 204 are affected by surroundings as equally as possible. From this reason, even in the dummy pixel region 203, a dummy line DL that causes the same parasitic capacitance effect as the adjacent scanning lines Gj is provided close to the excess region 202.
In the liquid crystal display panel having the configuration in FIG. 7, when an illumination inspection is carried out, a selection voltage is applied to all the scanning lines Gj and the dummy scanning line DG so that the scanning lines Gj and the dummy scanning line DG are in a selection state, and all the test TFTs 201b are caused to be in an ON state by the test switch line 201a. Then, signals respectively supplied to the test data lines 201R, 201G, and 201B are written to a respective of the pixels via the data lines Si.
[Patent Document 1]
    Japanese Unexamined Patent Publication, Tokukai, No. 2005-122209 (published on May 12, 2005)[Patent Document 2]    Japanese Unexamined Patent Publication, Tokukaihei, No. 1′-149092 (published on Jun. 2, 1999)[Patent Document 3]    Japanese Unexamined Patent Publication, Tokukaihei, No. 9-80478 (published on Mar. 28, 1997)